As devices scale down to the sub-micron level, electrical characteristics such as capacitance that were negligible in devices having dimensions in multiples of microns, have become significant. For example, in a sub-0.20 .mu.m process there has been a renewed interest in materials with a low dielectric constant (i.e., "low k").
A goal in processing sub-micron devices is to maintain a level of gate capacitance while minimizing the gate-to-source and gate-to-drain capacitance. As the oxide is made thinner the capacitance increases as shown in the relationship: ##EQU1##
where
A=area of gate
.epsilon..sub.SiO.sub..sub.2 =dielectric constant (or relative permittivity of SiO.sub.2 taken as 3.9)
t.sub.ox =oxide thickness
The gate-to-drain capacitance is especially critical for transistor performance as it is amplified during switching due to the Miller effect. For example, in a series of logic stages, the equivalent capacitive loading to the previous logic stage is the gate-to-source capacitance multiplied by a factor of 1 plus the gain of the transistor. If the transistor has a gain of 100, the observed input capacitance would be 101 times the gate-to-drain capacitance. Consequently, it is desirable to not alter the parameters that tend to increase that capacitance. Therefore, using a dielectric material having a lower dielectric constant lowers the capacitance. It is advantageous to use lower k materials throughout the integrated circuit design where possible to minimize the parasitic capacitance.
The requirement for low k materials for sub-quarter micron and smaller devices has renewed the interest in spin-on dielectrics such as methyl silsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ). MSQ has a dielectric constant of .about.2.9. The empirical formula of MSQ is CH.sub.3 SiO.sub.1.5. The addition of organic side groups to the basic O--Si--O backbone results in improved crack resistance of the films. The structure has a lower density and hence a lower dielectric constant than that of SiO.sub.2.
In an example process, it is a challenge to integrate MSQ as a low k dielectric. MSQ and PECVD (plasma enhanced chemical vapor deposition) oxide do not adhere well to one another owing to the presence of methyl groups on the surface. The material has significant methyl content up to about 25%. The presence of methyl groups makes the film hydrophobic, as it is difficult to form SiOH bonds by breaking the Si--CH.sub.3 bonds.
FIG. 1 depicts a substrate 100 having metal lines 110. The de-lamination of MSQ 130 from the liner oxide 120 may degrade performance of the device
There exists a need to provide for the adhesion of MSQ to the PECVD oxide that resists de-lamination enabling the use of this low k dielectric to improve device yield and product performance.